In the manufacture of integrated circuit memory devices it is necessary to test the memory devices for the presence of physical faults (e.g., short circuits, opens or other physical or electrical faults) that may occur in memory bit cells during the manufacturing process. Much effort is made to correlate the faults to fabrication processes for yield and manufacturing improvement, driving large capital expenditures. The systems involved are complex and include many aspects of the manufacture of the device. This includes inline defect monitoring, metrology, electrical test, full functional testing with bitmapping, failure analysis and complex mappings between each of the systems. The setup and verification of these systems traditionally can take months, and incur full project and technology delays, many months of human resources, and tens of thousands of dollars in failure analysis costs.
Prior art methodologies do not provide for the rapid setup and verification of the many components necessary for a fully operational, verified, and complete system for understanding and driving improvements in the manufacture and test of the integrated circuits.
Therefore, there is a need in the art for an improved system and method for the setup of the various components for yield improvement, metrology, electrical test, full functional testing, bitmapping, and failure analysis of integrated circuits containing memory devices.